IGNIS Design Engineer to present paper at PRIME 2017

2月 15, 2017

Jafar Talebzadeh, IGNIS Innovation’s Principal Analog Mixed Signal IC Design Engineer, is going to present a paper at the PRIME 2017 conference in Bariloche, Argentina (Feb. 20-23). His paper title is “Design of a Delayless Feedback Path Free 2nd-order Two-Path Time-Interleaved Discrete-Time Delta-Sigma Modulator – a New Approach”. An Abstract of Jafar’s paper follows:


“This paper presents the design procedure for a 2nd-order two-path Discrete-Time Time-Interleaved (DTTI) Delta Sigma modulator from a conventional single-loop 2nd-order Discrete-Time (DT) Delta Sigma modulator through the use of time domain equations and time-interleaving concepts. The resulting modulator is free from the delayless feedback path and has only one set of integrators. The delayless feedback path issue in Time-Interleaved (TI) Delta Sigma modulators is a critical restriction for the implementation of TI Delta Sigma modulators and is effectively eliminated through the use of the approach proposed in this paper. The DTTI Delta Sigma modulator requires only three op-amps and two quantizers both of which work concurrently, in comparison to the single-loop DT counterpart that also deploys two op-amps. For an OverSampling Ratio (OSR) of 16 and a clock frequency of 640MHz, our simulation results show a maximum Signal-to-Noise Ratio (SNR) for the DTTI Delta Sigma modulator to be 70.5dB with an input bandwidth of 20MHz which has 15dB improvement in comparison to its single-loop, single-path DT counterpart”.